1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, a method of and an apparatus for reducing current flow from a power supply into a memory device immediately after the power supply is turned on.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a memory board generally employed in apparatuses utilizing computers. Referring to FIG. 1, the memory board 40 comprises a number of memory chips 1 for storing data signals and a control circuit 41 for controlling the memory chip 1. The memory chip 1 is connected to receive voltage from an external power supply V.sub.CC1 through a terminal 42 and the control circuit 41 is connected to receive a voltage from another external power supply V.sub.CC2 through a terminal 43. The control circuit 41 generates a RAS (Row Address Strobe) signal, a CAS (Column Address Strobe) signal and address signals, and controls reading/writing of the memory chip 1 based on instructions from a CPU (Central Processing Unit).
In order to supply power to the memory chip 1 and the control circuit 41, different power supplies V.sub.CC1 and V.sub.CC2 such as shown in FIG. 1 are utilized, or a common power supply is utilized. For example, if a backup power supply for a memory chip 1 is used, two different supply voltages are applied. In either case, the level (high or low) of the RAS signal applied to the memory chip 1 depends on the system when the power is turned on.
FIG. 2 is a block diagram showing a conventional 1 M-bit dynamic RAM (Random Access Memory Device). The dynamic RAM such as shown in FIG. 1 is disclosed in "A reliable 1-M bit DRAM with a multi-bit-test mode" by M. Kumanoya et al., 1985 (IEEE Journal Solid-State Circuits, vol. SC-20, pp. 909-913) and also in "A Fast 256K.times.4 CMOS DRAM with a Distributed Sense and Unique Restore Circuits" by H. Miyamoto et al., 1987 (IEEE Journal Solid-State Circuits, vol. SC-22, pp. 861-867).
Referring to FIG. 2, the dynamic RAM comprises a clock generator circuit 10 for outputting clock signals .phi..sub.1 and .phi..sub.2 which control this dynamic RAM in response to a CAS signal and a RAS signal. The CAS signal and the RAS signal are externally applied through a CAS terminal 8 and a RAS terminal 4, respectively. A power supply V.sub.CC (5 V) and the ground V.sub.SS (0 V) are externally applied through a power supply terminal 2 and a ground terminal 3, respectively.
FIG. 3 is a timing chart showing the change of the current to be consumed in the dynamic RAM. Referring to FIG. 3, the dynamic RAM has two states of operation, that is, standby state and active state. The dynamic RAM is brought to the standby state when a high level RAS signal is applied, while it is brought to the active state when a low level RAS signal is applied. As is apparent from the figure, the current Icc to be consumed flowing from the power supply (V.sub.CC shown in FIG. 2) changes dependent on the state of operation of the dynamic RAM.
In the standby state, an approximately constant current I.sub.2 of about 1.about.3 mA flows from the power supply V.sub.CC to the dynamic RAM. (The reason for this will be described later.)
Immediately after the change of the RAS signal from high level to low level, the dynamic RAM is brought to the active state and a transient current I.sub.a flows. The current I.sub.a mainly comprises a charging current for activating the clock generator circuit 10 and an operating current for operating the row address buffer 21 and the row decoder 22 in FIG. 2. After 30.about.50n sec from the change of the RAS signal to the low level, a transient current I.sub.b flows. The current I.sub.b is consumed by the sense amplifier 24 to charge bit lines in the memory array 25. The bit line charging operation by the sense amplifier 24 in the active state will be described in detail later.
When the current I.sub.b is decreased, a constant current I.sub.4 flows to activate the data output buffer 27. The current I.sub.4 is less than 10 mA in a normal state.
Thereafter, immediately after the change of the RAS signal from the low level to the high level, the dynamic RAM returns to the standby state and a transient current I.sub.c flows. The current I.sub.c mainly comprises a current for bringing the clock generator circuit 10 to the standby state and a current for bringing the row address buffer 21 and the row decoder 22 to the standby state.
FIG. 4 is a schematic diagram showing the clock generator circuit of the dynamic RAM in FIG. 2. Referring to FIG. 4, the clock generator circuit 10 comprises a buffer circuit connected to a RAS terminal 4 and a inner circuit 11 connected between a power supply V.sub.CC and the ground VSS for outputting clock signals .phi..sub.1 and .phi..sub.2 in response to a signal from the buffer circuit. The buffer circuit comprises two inverters 5a and 5b connected in series. A reference character Icc represents consumed
current flowing from the power supply V.sub.CC to a dynamic RAM 1.
In general, for a circuit receiving an input signal from the outside, a buffer circuit connected to an input terminal comprises inverters. For example, a buffer circuit employing inverters is described by Neil H. E. Weste et al. in "PRINCIPLES OF CMOS VLSI DESIGN", pp. 227-229, published by ADDISON-WESLEY PUBLISHING COMPANY in 1985.
A description is given of operation which occurs when the supply voltage V.sub.CC is externally applied to the dynamic RAM in FIG. 4.
FIGS. 5 and 6 are timing charts showing a change of signals for explaining the operation of the dynamic RAM in FIG. 4. Referring to FIGS. 5 and 6, the supply voltage V.sub.CC starts to be applied to the terminal 2 from a time t.sub.1 and the applied voltage rises up to a predetermined voltage level. When the applied voltage reaches the predetermined voltage level, it will not change thereafter.
FIG. 5 shows the case in which a high-level RAS signal is applied to the RAS terminal 4 before the time t.sub.1. The dynamic RAM is in the standby state when the RAS signal is at high level and it is in the active state when the RAS signal is at low level. Power consumption is small when the dynamic RAM is in the standby state and it is large when the dynamic RAM is in the active state. Therefore, the supply voltage V.sub.CC (for example 5 V) is applied to the dynamic RAM while the dynamic RAM is in the standby state in FIG. 5. As a result, after the current Icc flowing into the dynamic RAM reaches its small peak value of I.sub.1 (several mA) at a time t.sub.2, the value is reduced to I.sub.2 which is smaller than I.sub.1, and then stabilized. The value of I.sub.2 is a current value necessary for operation in the standby state. The reason why these different values flow will be described in the following.
FIG. 7 is a schematic diagram showing a buffer circuit in the clock generator circuit 10 shown in FIG. 4. Referring to FIG. 7, the buffer circuit comprises two inverters 5a and 6a. The inverter 5a comprises a series connection of a P channel MOS transistor Q1 and an N channel MOS transistor Q2 connected between the power supply V.sub.CC and the ground V.sub.SS . The gates of the transistors Q1 and Q2 are connected together and the RAS signal is applied thereto. The inverter 5b also comprises a P channel MOS transistor Q3 and an N channel MOS transistor Q4 connected in a similar manner as the inverter 5a. The gates of the transistors Q3 and Q4 are connected together to the output of the inverter 5a. A stray capacitance C10 exists between the output node N10 of the inverter 5a and the ground V.sub.SS, and a stray capacitance C11 exists between the output node N11 of the inverter 5b and the ground V.sub.SS.
FIG. 8 is a timing chart showing the change of the voltage at output nodes of two inverters shown in FIG. 7 when the power supply V.sub.CC rises. Referring to FIGS. 7 and 8, the nodes N10 and N11 are at 0 V before the voltage of the power supply V.sub.CC rises. When the power supply V.sub.CC rises after a high level RAS signal is applied, the output node N10 of the inverter 5a remains at 0 V. Meanwhile, the output node N11 of the inverter 5b is brought to a high level voltage, so that the stray capacitance C11 existing between the node N11 and the ground V.sub.SS is charged. Therefore, a charging current flows from the power supply V.sub.CC.
Various peripheral circuits are provided in the dynamic RAM as shown in FIG. 2, each of which comprising, in most cases, circuits such as shown in FIG. 7. As described above, immediately after the power supply V.sub.CC is turned on, charging currents for charging stray capacitances in these circuits flow in, causing a peak current I.sub.1 at the time t.sub.2 shown in FIG. 5.
Referring again to FIG. 7, the current I.sub.2 of a constant value consumed after the time t.sub.2 will be described. The current I.sub.2 corresponds to the current I.sub.2 from the power supply V.sub.CC which is shown in FIG. 3.
Generally, the RAS signal has a voltage level called TTL (Transistor Transistor Logic) level. More specifically, the high level of the RAS signal is about 2.4 V when the power supply V.sub.CC is 5 V. The transistor Q2 turns on in response to a high level RAS signal applied between the gate and the source thereof. Meanwhile, the transistor Q1 receives approximately -2.6[=-(V.sub.CC -2.4)]V between the gate and the source thereof, and turns on. Therefore, both transistors Q1 and Q2 turn on and a current flows from the power supply V.sub.CC to the ground V.sub.SS . This current is included in the current I.sub.2 shown in FIG. 5, which flows constantly. In addition, a current which will be described in the following is also included in the current I.sub.2.
FIG. 9 is a schematic diagram showing a ring oscillator provided for generating negative voltage in the dynamic RAM. Referring to FIG. 9, the ring oscillator comprises an odd-number of inverters 29 which is connected in series to form a ring. A pulsating current which fluctuates in several mega-hertz frequency flows into the ring oscillator from the power supply V.sub.CC. Since this current is of high frequency, it seems as a direct current and is included in the current I.sub.2 shown in FIG. 5.
On the other hand, the timing chart of the FIG. 6 shows the case in which the supply voltage V.sub.CC starts to be applied to the dynamic RAM from the time t.sub.1, while the RAS signal is low level. Since the supply voltage V.sub.CC is applied to the RAM chip while the RAM chip is in the active state, the current Icc after the time t.sub.1 is increased. At this time, since each node of circuits in the dynamic RAM has not been necessarily brought to a predetermined high or low level, excessive current Icc flows therein. As a result, after the current Icc reaches its big peak value of I.sub.3 (several tens of mA) which is bigger than the value of I.sub.1 at the time t.sub.3, it is reduced to the value of I4 (below 10 mA) which is considerably smaller than the value of I.sub.3, and then stabilized. The value of I.sub.4 is a current value necessary for operation in the active state, which is the same as that shown in FIG. 3.
A description is given of the reason for the inflow of the excessive current hereinafter.
FIG. 10 is a schematic diagram showing an example of portions of the sense amplifier 24 and the memory array 25 of the dynamic RAM bit line shown in FIG. 2. Referring to FIG. 10, the sense amplifier 24 comprises two latch circuits connected between a bit line 241 and a bit line 242. One latch circuit is constituted by N channel MOS transistors Q10 and Q11 and is connected to the ground V.sub.SS through an N channel MOS transistor Q12. The other circuit is constituted by P channel MOS transistors Q13 and Q14 and is connected to the power supply V.sub.CC through a P channel MOS transistor Q15. The gates of the transistors Q12 and Q15 are connected such that they receive sense signals .phi..sub.s and .phi..sub.s respectively, which signals are inverted from each other.
The memory array 25 is connected to the sense amplifier 24 through the bit lines 241 and 242. Memory cells MC each consisted of one N channel MOS transistor and a capacitor are connected between the bit line 241 or 242 and the word line 243. There are stray capacitances C.sub.B1 and C.sub.B2 between respective bit lines 241 and 242 and the ground V.sub.SS.
FIG. 11 is a timing chart showing the operation of a circuit shown in FIG. 10 when the power supply V.sub.CC rises after a high level RAS signal is applied (in this case, it corresponds to the case shown in FIG. 5). Referring to FIGS. 10 and 11, the bit lines 241 and 242 are at 0 V before the power supply V.sub.CC rises. When a high level RAS signal is applied and the power supply V.sub.CC rises, a sense signal .phi..sub.s of 0 V is applied to the gate of the transistor Q12. Therefore, the transistor Q12 remains off.
Meanwhile, a sense signal .phi..sub.s which goes to a high level from 0 V simultaneously with the rise of the power supply V.sub.CC is applied to the gate of the transistor Q15. Therefore, the transistor Q15 also remains off. Since both transistors Q12 and Q15 are off, the stray capacitances C.sub.B1 and C.sub.B2 are not charged. That is, the bit lines 241 and 242 are not charged by the power supply V.sub.CC, and no current flows in from the power supply V.sub.CC.
FIG. 12 shows a timing chart in which the power supply V.sub.CC rises while the RAS signal remains at low level (corresponding to the case shown in FIG. 6). Referring to FIGS. 10 and 12, the bit lines 241 and 242 are at 0 V before the rise of the power supply V.sub.CC. A sense signal .phi..sub.s which has risen to a high level from 0 V simultaneously with the rise of the power supply V.sub.CC is applied to the gate of the transistor Q12. Therefore, the transistor Q12 turns on. Meanwhile, a sense signal .phi..sub.s of 0 V is applied to the transistor Q15, and the transistor Q15 also turns on. Since both transistors Q12 and Q15 are turned on, current flows into the bit lines 241 and 242 from the power supply V.sub.CC through the transistor Q15 and to the ground V.sub.SS through the transistor Q12. The voltages at the bit lines 241 and 242 are slightly increased from 0 V due to this current. On this occasion, a through current flows from the power supply V.sub.CC to the ground V.sub.SS through the transistor Q15, Q13 or Q14, Q10 or Q11, and Q12.
Thereafter, since the sense amplifier 24 comprises two latch circuits as described above, the bit line 241, for example, is brought to a high level and the bit line 242 is brought to a low level. Which of the two bit lines 241 and 242 is brought to the high level is determined by a slight imbalance between the stray capacitances C.sub.B1 and C.sub.B2 having approximately the same capacitance value. Since one of the two bit lines 241 and 242 is charged by the power supply V.sub.CC, a charging current flows into the dynamic RAM from the power supply V.sub.CC. Generally, one stray capacitance C.sub.B1 or C.sub.B2 has a value less than 0.4 pF. Therefore, in a case of 1 mega-bit dynamic RAM, for example, 2048 stray capacitances are charged, with the total capacitance value being 819 pF (=0.4 pF.times.2048). A current for charging the total capacitance is included in the current I.sub.3 shown in FIG. 6.
The current I.sub.3 shown in FIG. 6 comprises the following current besides the above described through current and the charging current from the power supply V.sub.CC. Referring again to FIG. 7, when the power supply V.sub.CC rises with the RAS signal being low level, the output node N10 of the inverter 5a is brought to a high level voltage from 0 V. Therefore, the stray capacitance C10 existing between the node N10 and the ground V.sub.SS is charged by the power supply V.sub.CC and a charging current flowing in from the power supply V.sub.CC . As described above, the dynamic RAM comprises a number of circuits such as shown in FIG. 7 and such charging currents are included in the current I.sub.3 shown in FIG. 6.
Meanwhile, the constant current I.sub.4 which flows after the time t.sub.3 corresponds to the current I.sub.4 of the timing chart shown in FIG. 3.
As described above, in the conventional dynamic RAM, the excessive current I.sub.3 (for example 50 mA) from the power supply V.sub.CC flows in when the power supply V.sub.CC is turned on. Because of this excessive current I.sub.3, power supply capacity could be insufficient, so that other circuits could not operate correctly or the line fuse could be blown.
In addition, the excessive current I.sub.3 may possibly cause a latch-up in the substrate of the dynamic RAM as will be described in the following.
FIG. 13A is a cross sectional view showing the structure of a conventional CMOS inverter on a substrate. A number of CMOS inverters such as shown in the figure are included in the peripheral circuit of the dynamic RAM.
Referring to FIG. 13A, the substrate bias voltage V.sub.BB is applied to a p type silicon substrate 30 through a substrate bias conductor 35. The substrate bias voltage (hereinafter simply referred to as V.sub.BB) is generated from a V.sub.BB generating circuit 29 provided on the RAM chip. A p channel MOS transistor Q5 is formed in an n-well 31 formed in the p type silicon substrate 30. An n.sup.+diffused layer 32 serves to fix a voltage of n-well 31 to the supply voltage V.sub.CC' which is connected to a V.sub.CC power supply conductor. An n.sup.+ diffused layer 33 is formed in the p type silicon substrate 30 and it is connected to the V.sub.CC power supply conductor. An n.sup.+ diffused layer 34 is formed in the p type silicon substrate 30 and it is connected to a ground conductor V.sub.SS.
As seen from the drawing, a p-n junction capacitance C.sub.WELL formed between the n-well 31 and the p type silicon substrate 30 and a p-n junction capacitance Cn.sup.+ formed between the n .sup.+ diffused layer 33 and the p type silicon substrate 30 form a component of the parasitic capacitance.
FIG. 13B is an equivalent circuit of the peripheral circuit shown in FIG. 13A and prepared for explaining parasitic bipolar transistors and a parasitic capacitance being parasitic on the dynamic RAM.
Referring to FIG. 13A and 13B, a mechanism of the latching-up is explained. The peripheral circuit comprises a parasitic bipolar transistor Tr.sub.1 (pnp transistor) coupled between the power supply conductor V.sub.CC and the V.sub.BB generating circuit through resistance R.sub.2, a parasitic bipolar transistor Tr.sub.2 (npn transistor) coupled between the power supply conductor V.sub.CC through a resistance R.sub.1 and the ground conductor V.sub.SS, a total parasitic capacitance C.sub.P coupled between the power supply conductor V.sub.CC and the V.sub.BB generating circuit, and the V.sub.BB generating circuit coupled between the power supply conductor V.sub.CC and the ground conductor V.sub.SS . The substrate bias V.sub.BB generating circuit is provided to provide a predetermined negative bias voltage to the substrate.
The transistor Tr.sub.1 comprises a p.sup.+ diffusion layer in an n-well, an n.sup.+ diffusion layer 32 in the n-well and the substrate itself. The transistor Tr.sub.2 comprises an n.sup.+ diffusion layer 34, the substrate itself and n.sup.+ layer 32 in the n-well. The C.sub.WELL is formed between n-well 31 and the substrate 30. The V.sub.BB generating circuit 29 usually keeps the substrate at -3 V. A reversed bias is applied between a base and an emitter of the transistor Tr.sub.2 . The transistor Tr.sub.2 is in off state. Therefore, no voltage is applied between the base and the emitter of the transistor Tr.sub.1 and the transistor Tr.sub.1 is also in off state.
The substrate 30 is brought to a positive potential when currents are flowing from the power supply V.sub.CC. Therefore, a forward bias voltage is applied to the p-n junction in the substrate, causing a latch-up. Namely, since the forward bias voltage is applied between the base and the emitter of the transistor Tr.sub.2, the transistor Tr.sub.2 turns on. A current flows from the power supply conductor V.sub.CC to the ground conductor V.sub.SS through the resistance R.sub.1 and the transistor Tr.sub.2. As there is the resistance R.sub.1 in the substrate, potential drops occur and a forward bias voltage is applied between the base and the emitter of the transistor Tr.sub.1. As a result, the transistor Tr.sub.1 turns on. A current flows to the base of the transistor Tr.sub.2 and the transistor Tr.sub.2 is kept turned on (corresponding to the state .circle.1 shown in FIG. 13B). As there is the resistance R.sub.1 in the substrate, the transistor Tr.sub.1 is kept turning on (corresponding to the state .circle. 2 shown in FIG. 13B). States .circle.1 and .circle.2 occur continuously and a current continues to flow from the power supply conductor V.sub.CC to the ground conductor V.sub.SS . This phenomenon is called a latch-up. In order to prevent the latch-up phenomenon, a substrate bias voltage generating circuit which will be described in the following is provided to bring the substrate 30 to a negative potential.
FIG. 14A is a schematic diagram showing one example of a conventional V.sub.BB generating circuit. Referring to FIG. 14A, the V.sub.BB generating circuit comprises a ring oscillator 291 having an odd-number of inverters connected in a ring, and a charge pump circuit 292 connected to the output of the ring oscillator 291. The charge pump circuit 292 comprises a charge pump capacitor C.sub.A and two n channel transistors Q21 and Q22.
FIG. 14B is a timing chart for illustrating the operation of the V.sub.BB generating circuit shown in FIG. 14A. The figure shows changes of an output signal .phi..sub.R of the ring oscillator 291, the potential of a node N.sub.A between the transistors Q21 and Q22 and of the output voltage V.sub.BB. The operation will be described with reference to FIGS. 14A and 14B.
First, when a voltage signal at a rise of the output signal .phi..sub.R of the ring oscillator 291 is applied to the charge pump capacitor C.sub.A (time tll), the potential at the node N.sub.A rises due to the capacitive coupling. Then the transistor Q21 turns on, whereby the potential of the node N.sub.A is clamped at the threshold voltage V.sub.TH of the transistor Q21 (time t.sub.12) When a voltage signal at a fall of the signal .phi..sub.R is applied to the capacitor C.sub.A (time t.sub.13), the potential at the node N.sub.A is decreased due to the capacitive coupling. However, at this time the transistor Q22 turns on, whereby the output voltage V.sub.BB decreases and the potential at the node NA is clamped at a negative potential which is equal to the threshold voltage V.sub.TH of the transistor Q22 (time t.sub.14). By the repetition of such cycle, the output voltage V.sub.BB is decreased to reach a prescribed voltage required as the substrate bias voltage.
FIG. 14C is a graph showing a relation between the output voltage and the number of pulses generated by the oscillation in the V.sub.BB generating circuit shown in FIG. 14A. Referring to FIG. 14C, the maximum amount of charges Q.sub.MAX pumped by the capacitor C.sub.A at one oscillation of the ring oscillator 291 will be EQU Q.sub.MAX =C.sub.A.(V.sub.CC -2V.sub.TH) (1)
where V.sub.CC is a supply voltage and C.sub.A is the capacitance value of the capacitor C.sub.A. Therefore, the output voltage V.sub.BB obtained by N times of oscillation will be EQU V.sub.BB .ltoreq.(Q.sub.Max /C.sub.SUB).N (2)
where, C.sub.SUB represents all p-n junction capacitances in the dynamic RAM such as the capacitances C.sub.WELL and C.sub.n + formed between the p type substrate 30 and the n-well 31 and the n+ diffusion layer 33. Consequently, the V.sub.BB generating circuit outputs the voltage of about -(V.sub.CC -2V.sub.TH).
Although the V.sub.BB generating circuit is provided to prevent the latch-up, it requires much time after the power supply V.sub.CC turn on to output a prescribed voltage, as shown in FIG. 14C. Therefore, it cannot always prevent a latch-up caused by the excessive current I.sub.3 immediately after the power supply V.sub.CC is turned on.